Traditional synchronous circuit designs are represented using a variety of hardware description languages, higher level description languages, netlists, and schematics. All of these synchronous representations define the functionality of the circuits in the presence of a clock signal or with a master timing signal used to synchronize operations. To utilize an asynchronous architecture to implement the same synchronous circuit, the synchronous representation must be translated into an asynchronous representation. To accomplish this goal, there have been generally known to be two fundamental approaches:
1) Redesign the circuit using an asynchronous representation.
2) Convert the existing synchronous representation into an asynchronous representation.
Approach (1) above is time intensive and involves re-implementing an entire design for execution in an asynchronous architecture. This is an approach that is not generally acceptable to designers. It is costly in terms of time and requires that designers learn a completely new way to represent circuit designs; in an asynchronous format. The field of asynchronous design is an old field encompassing significant prior art.
Approach (2)—converting an existing synchronous representation into an asynchronous representation—is an approach the present inventors believe would be both valuable to and favored by circuit designers if such an approach did not require any knowledge of asynchronous circuits by the designer.
Automated conversion of synchronous circuit designs to asynchronous representations have been discussed, but to the best knowledge of the inventors, has never been implemented in an effective, commercially viable solution. No existing art addresses the problem of converting synchronous circuit designs in the presence of multiple clock domains, latches and flip-flops (positive and negative triggered), and clock gating. No existing art exists, to the best knowledge of the inventors, which can generate asynchronous conditional block designs from synchronous designs. Also, there is no prior work known to the inventors whereby to convert a synchronous system into an asynchronous design while preserving the illusion of synchrony on the primary inputs and outputs.